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Contact Name  | Contact Details | Job Title | Company Name |
|---|---|---|---|
SS Shaileshkumar Shingala |  Phone Email | Vice President (FPGA RTL Design & Verification) |  JPMorgan Chase |
PN Padma Nagarajaa | PhoneEmail | Director, Enterprise Storage Systems ASIC & FPGA Design |  IBM |
TL Thiam Lim | PhoneEmail | Director, Unified Core FPGA & Post-Silicon Design Verification |  Intel |
NH Nimrod Hagay | PhoneEmail | Senior Director, FPGA Logic Design |  Rafael |
AA Abdul Afaghani | PhoneEmail | Manager, FPGA Design |  Cisco |
JG John Garro | PhoneEmail | Digital, FPGA & Embedded Design Manager, Electrical Engineering |  V2X |
FB Fan Bu | PhoneEmail | Manager, Digital IP Design FPGA & Soc Integration |  Lattice Semiconductor |
KH Kang Huang | PhoneEmail | Manager, FPGA Design |  Compal Electronics |
CW Chase Weimer | PhoneEmail | Manager, FPGA Soc Design Section & Embedded Design Engineer |  Leidos |
SB Shelly Blandon | PhoneEmail | Manager, ASIC & FPGA Design |  Lockheed Martin |
LW Lizhong Wang | PhoneEmail | Manager of FPGA and Driver Design |  Ericsson |
US Uzi Shamriz | PhoneEmail | FPGA Architecture Design and FPGA Team Management |  Radware |
YP Yossi Peled | PhoneEmail | Group Manager, FPGA Design |  Elbit Systems |
MM Martin Mavis | PhoneEmail | Manager, ASIC & FPGA Design Engineering | Lockheed Martin |
JR Jacqueline Raetzsch | PhoneEmail | Senior Principal Electrical Engineer, FPGA Designer and Section Manager |  RTX |
VN Vahid Naraghi | PhoneEmail | Senior Manager, FPGA Design |  Ciena |
HD Heping Du | PhoneEmail | Manager, FPGA Design |  Shanghai STEP Electric |
MS Matthew Schultz | PhoneEmail | Manager, FPGA Design Engineering |  Extron |
DR David Roddy | PhoneEmail | Manager, FPGA & Digital Circuit Design |  BAE Systems |
FF Ferdie Fajardo | PhoneEmail | Manager, Silicon Integration FPGA Design | Lattice Semiconductor |
