Contacts
Likely to Engage Contact 
Contact Name And Email
Current Role
Contact Info
Companies
Company Name/URL/Ticker
Industry
Employee Count
Revenue
Locations
Location
Contact Numbers and Email Addresses of B2B Business Professionals
Powered by 
Contact
Company
Browse Verified Professional Emails and Phone Numbers – Accurate & Up-to-Date
Build targeted lists and connect with verified professionals using ZoomInfo’s contact database. With over 209 million professional profiles and 13 million businesses, we offer more verified email addresses and direct phone numbers than any other market intelligence platform.
Contact Name  | Contact Details | Job Title | Company Name |
|---|---|---|---|
OR Ofir Rozmarin |  Phone Email | Director, IP Design Verification, Ethernet Silicon Engineering |  Intel |
BS Baruch Schnarch | PhoneEmail | Senior Director, Engineering Core Design Verification, Dfx, Fg & Post-Silicon System Validation | Intel |
SS Shubhra Singh | PhoneEmail | Director, Engineering, Analog Mixed Signal IP Design & Soc Ams Verification |  NXP |
TS Tsvi Staierman | PhoneEmail | Director, Design Verification Department & Manager & Product Manager, Engineering |  Nuvoton Technology Israel |
PL Ponnambalam Lakshmanan | PhoneEmail | Verification Engineering Director, Design |  Analog Devices |
PN Prathyusha Namburi | PhoneEmail | Director, Engineering Ai GPU Hardware Ips Design Verification & Execution | Intel |
SS S. Sarma Evani | PhoneEmail | Verification Engineering Director, Design | Analog Devices |
DS Deepak Sridhar | PhoneEmail | Director, Engineering, Design Verification |  Renesas Electronics |
RK Raman Kumar | PhoneEmail | Verification Engineering Director, Design | Analog Devices |
DH Dimpy Hasija | PhoneEmail | Manager, Design Verification Engineering | Intel |
YC Yahchen Chew | PhoneEmail | Manager, Design Verification Engineering | Intel |
DF Dan Fields | PhoneEmail | Manager, Engineering Responsible For Design & Functional Verification | Intel |
RM Rajesh Murugesan | PhoneEmail | Senior Manager, Engineering Soc IP Design, Verification & Emulation |  Microchip Technology |
AD Aditya Devarakonda | PhoneEmail | Global Manager, Engineering (Design Verification) | NXP |
PM Prasanth Mopuri | PhoneEmail | Senior Manager, Silicon Design Engineering, Amd Server Soc Performance Verification Lead |  AMD |
GN Gaurang Nagrecha | PhoneEmail | Manager, Soc Design Engineering Verification Validation Emulation | Intel |
HG Harini Gogineni | PhoneEmail | Senior Manager, Design Verification Engineering (Ams) | Analog Devices |
XZ Xuanlei Zhang | PhoneEmail | Engineering-Hardware Digital IC Design Verification Staff Engineer & Manager |  Marvell |
HD Hongwei Duan | PhoneEmail | Senior Principal Engineer & Senior Manager, SSD IP Design & Verification |  SK Hynix |
KT Kara Tervooren | PhoneEmail | Manager and Principal Engineer, Design Verification and Methodology | Analog Devices |
