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Contact Name  | Contact Details | Job Title | Company Name |
|---|---|---|---|
OR Ofir Rozmarin |  Phone Email | Director, IP Design Verification, Ethernet Silicon Engineering |  Intel |
BS Baruch Schnarch | PhoneEmail | Senior Director, Engineering Core Design Verification, Dfx, Fg & Post-Silicon System Validation | Intel |
TS Tsvi Staierman | PhoneEmail | Director, Design Verification Department & Manager & Product Manager, Engineering |  Nuvoton Technology Israel |
SS Shubhra Singh | PhoneEmail | Director, Engineering, Analog Mixed Signal IP Design & Soc Ams Verification |  NXP |
PN Prathyusha Namburi | PhoneEmail | Director, Engineering Ai GPU Hardware Ips Design Verification & Execution | Intel |
PL Ponnambalam Lakshmanan | PhoneEmail | Verification Engineering Director, Design |  Analog Devices |
SS S. Sarma Evani | PhoneEmail | Verification Engineering Director, Design | Analog Devices |
DS Deepak Sridhar | PhoneEmail | Director, Engineering, Design Verification |  Renesas Electronics |
RK Raman Kumar | PhoneEmail | Verification Engineering Director, Design | Analog Devices |
XZ Xuanlei Zhang | PhoneEmail | Engineering-Hardware Digital IC Design Verification Staff Engineer & Manager |  Marvell |
EG Eric Gonzales | PhoneEmail | Manager, CPU Design Verification Engineering | Intel |
DH Dimpy Hasija | PhoneEmail | Manager, Design Verification Engineering | Intel |
CS Chen Stone | PhoneEmail | Senior Manager, ASIC Design Verification & Engineer |  AMD |
YC Yahchen Chew | PhoneEmail | Manager, Design Verification Engineering | Intel |
DF Dan Fields | PhoneEmail | Manager, Engineering Responsible For Design & Functional Verification | Intel |
GZ Gonzalo Zoleta | PhoneEmail | Manager, Design Verification Engineer | Analog Devices |
SG Sunil Gathani | PhoneEmail | Manager, Digital IP Design Engineering (Design, Verification, Mixed-Signal Verification Msv) |  Microchip Technology |
RM Rajesh Murugesan | PhoneEmail | Senior Manager, Engineering Soc IP Design, Verification & Emulation | Microchip Technology |
AD Aditya Devarakonda | PhoneEmail | Global Manager, Engineering (Design Verification) | NXP |
PM Prasanth Mopuri | PhoneEmail | Senior Manager, Silicon Design Engineering, Amd Server Soc Performance Verification Lead | AMD |