Yakov Zbinovich This is Me

 Web References

1. 1. HyperTransport™ Consortium - Press Release

   www.gotheseus.com/consortium/c - [Cached]

   Published on: 7/18/2001   Last Visited: 11/26/2007

   Furthermore, since the processor is compliant with MIPS64, we can take advantage of industry standard tools and software written for the MIPS platform, thereby minimizing our overall development effort," said Yakov Zbinovich, Hardware Development Manager at Redback Networks.

2. 2. HyperTransport™ Consortium - Press Release

   www.hypertransport.org/consort - [Cached]

   Published on: 7/18/2001   Last Visited: 4/18/2007

   Furthermore, since the processor is compliant with MIPS64, we can take advantage of industry standard tools and software written for the MIPS platform, thereby minimizing our overall development effort," said Yakov Zbinovich, Hardware Development Manager at Redback Networks.

3. 3. Temple Of Technology

   www.templeoftech.com/press.cfm - [Cached]

   Published on: 7/18/2001   Last Visited: 3/16/2002

   Furthermore, since the processor is compliant with MIPS64, we can take advantage of industry standard tools and software written for the MIPS platform, thereby minimizing our overall development effort," said Yakov Zbinovich, Hardware Development Manager at Redback Networks.
   
   L2 Cache, DDR Memory Controller, and Integrated I/O
   
   Along with two high-performance CPUs, the BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 Gigabytes of memory with current generation memory chips. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport (formerly called LDT), a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and extensive on-chip debug features.