Prashant Saxena

Prashant Saxena, Intel Inc., USA

Prashant Saxena, Intel Corp, US

Prashant Saxena (psaxena) Intel CorporationPrashant works as a Staff CAD Engineer at the Strategic CAD Labs at Intel in Hillsboro, OR.His primary research interests are in signal integrity issues and the optimization and layout of high performance circuits.He obtained his Ph.D. in Computer Science in 1998 from the University of Illinois at Urbana-Champaign.

The 2003 ISPD paper was cited by the panel's leading "Chicken Little," Prashant Saxena, staff CAD engineer at Intel Labs."Exploding buffer counts will break today's IC design paradigm," he said."All realistic scaling projections encounter this problem."

There aren't easy solutions, Saxena said.Designers can shrink block sizes, but that just pushes the problem up to the chip assembly level.Designers can use fat wires, but that causes routing congestion."The problem is here to stay," he said.
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Surrounded by ostriches, Saxena had a question: where will the EDA tools come from to support all these proposed architectural changes?

"The EDA industry is solving today's problems tomorrow," Saxena said.