Dave Hanson

Dave Hanson agrees.He is the business unit manager, benchmark services, for PDF Solutions, a provider of yield-management services and a member of the initiative.Via failure rates are "a dominant driver" in SOC yields, he emphasizes."If you have 30% fewer vias, your via-limited yield component is going to be much less, and your overall yield is going to be much higher."

A process line with Manhattan-style yields will create more usable die with diagonal routing, Hanson adds.The percentage improvements in chip performance and the wiring reductions are parameters connected directly to yield, he notes.
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The use of diagonal wiring does pose some questions without answers at this time, Hanson says."There's a lot that's not clear" about which problems are "layout dependent," for instance, "or even what the electrical effects are ... on features that are primarily 45, angles.A lot of the chips fabricated today don't really have that."

Expanding on Fujimura's comments, Hanson says problems related to resistance and capacitance "make extraction and design-rule checking more complicated than they were in the past.For mixed-signal system-on-chip products, your ability to close timing and finish the chip off is driven by the analog yield-loss component.The analog blocks in these mixed-signal SOCs ... tend to limit the ability to bring the yield of the circuits up quickly.That yield is affected by the resistance and capacitance of the interconnect system, and because these things are running at diagonals, we don't know how accurate the resistance and capacitance are going to be."

Hanson sees confidence,perhaps warranted, perhaps not,among equipment manufacturers."The tool providers think they have answers.It takes some volume [of production] and some experience.It's hard to predict how much time is going to be required, but we anticipate a lot of activity next year."

'If you have 30% fewer vias . . . your overall yield is going to be much higher.', Dave Hanson, PDF Solutions
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"To be precise, for several years people have had the concept of the gridless router that makes bends, if you will," explains Hanson."That's been a useful technology, to a degree.

Dave Hanson agrees.He is the business unit manager, benchmark services, for PDF Solutions, a provider of yield-management services and a member of the initiative.Via failure rates are "a dominant driver" in SOC yields, he emphasizes."If you have 30% fewer vias, your via-limited yield component is going to be much less, and your overall yield is going to be much higher."

A process line with Manhattan-style yields will create more usable die with diagonal routing, Hanson adds.The percentage improvements in chip performance and the wiring reductions are parameters connected directly to yield, he notes."If you can get a 30% reduction in die area, that's also going to mean a huge impact in terms of the gross die per wafer that are going to be created.So even at the same yield rate, you're going to get more product per wafer."

In its work PDF has noted a new problem occurring with chips at the 0.25-µm node and below, what Hanson calls "layout-dependent yield loss.We focus mainly on that area, as opposed to concentrating on random defects."A number of techniques, including OPC and phase-shifting masks, can be used to correct such "pattern-dependent" yield loss.
...
The use of diagonal wiring does pose some questions without answers at this time, Hanson says."There's a lot that's not clear" about which problems are "layout dependent," for instance, "or even what the electrical effects are...on features that are primarily 45° angles.A lot of the chips fabricated today don't really have that."

Expanding on Fujimura's comments, Hanson says problems related to resistance and capacitance "make extraction and design-rule checking more complicated than they were in the past.For mixed-signal system-on-chip products, your ability to close timing and finish the chip off is driven by the analog yield-loss component.The analog blocks in these mixed-signal SOCs...tend to limit the ability to bring the yield of the circuits up quickly.That yield is affected by the resistance and capacitance of the interconnect system, and because these things are running at diagonals, we don't know how accurate the resistance and capacitance are going to be."

Hanson sees confidence-perhaps warranted, perhaps not-among equipment manufacturers."The tool providers think they have answers.It takes some volume [of production] and some experience.It's hard to predict how much time is going to be required, but we anticipate a lot of activity next year."

'If you have 30% fewer vias . . . your overall yield is going to be much higher.' - Dave Hanson, PDF Solutions

DuPont Photomasks (DPI) will be among the busy companies.
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"To be precise, for several years people have had the concept of the gridless router that makes bends, if you will," explains Hanson."That's been a useful technology, to a degree.Before that, there was basically a square, and you had to optimize placement of standard cells.Now they've created an octagon for packing the standard cells together and then doing the routing with short-link bends and things on diagonal angles as well as long runs on 45° angles."

Diagonal architecture creates a huge amount of data, Hanson notes.Despite the hurdles, toolmakers think they can overcome any problems, he believes."I think the standard answer you'll find is that they can do all of this.