Dr. Samuel Broydo This is Me

 View all 11 references Web References

1. 1. MARCO FCRP Interconnect Center Points of Contact

   fcrp.src.org/about/boardandcom - [Cached]

   Published on: 7/28/2002   Last Visited: 7/22/2003

   Samuel Broydo, Applied Materials, Inc.

2. 2. Applied Materials. Press Releases. Archive 1996. pr-00023.html

   www.etec.com/newsroom/pr-00023 - [Cached]

   Published on: 6/14/2001   Last Visited: 5/26/2002

   "Our joint work with SGS-Thomson is progressing well," said Dr. Samuel Broydo, managing director of Core Technical Capabilities at Applied Materials. "We look forward to extending our PSI activities under this new agreement."
   
   The Advanced Interconnect PSI program encompasses numerous technologies: Dielectric CVD; via metallization using several PVD metal deposition processes as well as CVD aluminum and TiN; Etching technologies for oxide and metal films; and Chemical Mechanical Polishing (CMP) for oxide planarization. The interconnect structure lies above the transistor levels on a device, and involves a group of deposition, etch and planarization processes that are used repeatedly as the layers are built up. For example, in a five-level metal design the interconnect can comprise more than half of the total steps used in fabricating a semiconductor device.

3. 3. Applied Materials. Press Releases. Archive 1996. pr-00023.html

   www.appliedmaterials.com/newsr - [Cached]

   Published on: 5/24/1996   Last Visited: 4/4/2002

   "Our joint work with SGS-Thomson is progressing well," said Dr. Samuel Broydo, managing director of Core Technical Capabilities at Applied Materials. "We look forward to extending our PSI activities under this new agreement."
   
   The Advanced Interconnect PSI program encompasses numerous technologies: Dielectric CVD; via metallization using several PVD metal deposition processes as well as CVD aluminum and TiN; Etching technologies for oxide and metal films; and Chemical Mechanical Polishing (CMP) for oxide planarization. The interconnect structure lies above the transistor levels on a device, and involves a group of deposition, etch and planarization processes that are used repeatedly as the layers are built up. For example, in a five-level metal design the interconnect can comprise more than half of the total steps used in fabricating a semiconductor device.