Dr. Reza Arghavani

Reza Arghavani, Applied Materials

Reza Arghavani, Fellow, Applied Materialsreza arghavani@amat.com

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Dr. Reza Arghavani FellowApplied Materials

Reza Arghavani is a Fellow at Applied Materials.In 2002 Dr. Arghavani joined Applied Materials as Senior Director of Technology and later became a Distinguished Member of Technical Staff and Fellow.At Applied, he led a team responsible for creating a series of stress inducing dielectrics, which are currently in use in high volume manufacturing for both Logic and Non-Volatile Memory applications.Dr. Arghavani is currently focused on developing Thin Film Technologies to enable the sub-32nm node Logic/Non-Volatile Memories technology.

Prior to joining Applied, Dr. Arghavani worked at Intel Corporation in Logic Technology Development responsible for developing, manufacturing, and copy exactly transferring three generations of high performance microprocessor gate stack technology.He was also responsible for integration, yield analysis, and failure analysis of front and backend processes.

Dr. Arghavani graduated from University of California at Los Angeles with a Ph.D. in Physics.His thesis topic focused on the growth and characteristics of SiGe heterostructures deposited by molecular beam epitaxy.He holds 48 U.S. patents and has authored over 40 papers in technical journals.He has won numerous Corporate Achievement Awards and has two best paper awards.

Reza Arghavani graduated from the U. of California at Los Angeles with a PhD in physics.He is a Fellow at Applied Materials, currently focused on developing thin-film technologies to enable the sub-45/73nm node logic/nonvolatile memories technology.Applied Materials, 3050 Bowers Ave., Santa Clara, CA, 95054, United States; ph 408/986-7328, e-mail Reza.Arghavani@amat.com.

As Applied Materials Fellow Reza Arghavani explained, it's difficult to achieve consistent grain structure and orientation in such small areas, while even small variations in structure can affect electrical performance.
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As Arghavani put it, "the leading companies know what the answer is [for pMOS], but they aren't saying."Noble metals, such as platinum and iridium, have the desired work function and temperature tolerance, but are notoriously difficult to etch.Conductive oxides, such as iridium oxide, are unstable at high temperatures.

In metal-gate structures, as in polysilicon structures, there is a tendency for the effective work function to drift toward the middle of the band gap after anneal.Annealing in an oxidizing ambient reduces the work-function shift, again indicating oxygen vacancies in the dielectric as a possible cause [3].Arghavani pointed out that many metal integration difficulties might actually be resolved by the use of a replacement-gate scheme.Dual-metal schemes lose many of the advantages of a gate-first structure, as the first metal must be etched away before the second metal is deposited, potentially damaging the silicon (see Fig.1).

Amir Al-Bayati, Lori Washington, Li-Qun Xia, Mihaela Balseanu, Zheng Yuan, Mark Kawaguchi,Faran Nouri & Reza Arghavani, Applied Materials, Inc., USA

Reza Arghavani Fellow

Reza Arghavani, PhD.FellowApplied Materials