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Wrong Subramanian Iyer?

Subramanian S. Iyer

Professor

UCLA

HQ Phone:  (310) 443-7000

Direct Phone: (310) ***-****direct phone

Email: s***@***.edu

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I agree to the Terms of Service and Privacy Policy. I understand that I will receive a subscription to ZoomInfo Community Edition at no charge in exchange for downloading and installing the ZoomInfo Contact Contributor utility which, among other features, involves sharing my business contacts as well as headers and signature blocks from emails that I receive.

UCLA

325 Westwood Plaza

Los Angeles, California,90095

United States

Company Description

UCLA Anderson Forecast is one of the most widely watched and often-cited economic outlooks for California and the nation and was unique in predicting both the seriousness of the early-1990s downturn in California and the strength of the state's rebound since 1...more

Find other employees at this company (59,717)

Background Information

Employment History

Chief Technologist

Semiconductor Research and Development Center


Indian Institute of Technology , Bombay


Adjunct Professor of Electrical Engineering

Columbia University


Affiliations

IEEE

Treasurer


Chief Technologist & IBM

Fellow Microelectronics Division, IBM Systems& Technology Group Venue


Systems and Technology Group

IBM Fellow


IBM Corporation

IBM Fellow, Director System Scaling Technology


Sibond Inc

Founder


Education

Indian Institutes of Technology


Bachelor of Technology in Electrical Engineering

Indian Institute of Technology , Bombay


M.S.

Electrical Engineering

University of California at Los Angeles


Ph.D.

UCLA


Ph.D.

Electrical Engineering

University of California at Los Angeles


Web References(95 Total References)


Semiconductor Engineering .:. Why Use A Package?

semiengineering.com [cached]

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department-and a former fellow and director of the systems scaling technology department at IBM-sat down with Semiconductor Engineering to talk about the future of chip scaling.
What follows are excerpts of that conversation. SE: Advanced packaging is being viewed as a way to extend scaling in the future. What's your view? Iyer: There are a few key things happening. Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million. Iyer: That has been the model for shrinking features in a silicon chip. Iyer: Any time you build a new SoC, you're basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before. Iyer: We're going to make these pieces hard IP. Iyer: That's one of the big technology projects. We're looking at it. Iyer: SerDes speed has been going up exponentially. Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements. SE: Then what happens to the package? Iyer: You have to ask yourself, what is this package really doing? Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we're going to test these die at full spec. SE: So what happens without a package? Iyer: You get rid of a huge amount of space. Iyer: By replacing the board with a silicon wafer. Iyer: In one sense, yes, because you can optimize the technology for each die-let. Iyer: Yes. Iyer: The supply chain does become more complicated. Iyer: That's the million-dollar question. Iyer: An interposer doesn't eliminate the package.


Insights From Leading Edge » 2016 » December

semimd.com [cached]

"Heterogeneous SoCs" - Professor Subramanian Iyer, UCLA


IWLPC - International Wafer Level Packaging Conference

iwlpc.com [cached]

Subramanian Iyer
Subramanian Iyer, Ph.D. Distinguished Chancellor's Professor Electrical Engineering Department University of California, Los Angeles


IMAPS 2017, RALEIGH - Technical Program

www.imaps.org [cached]

Subramanian S. Iyer (Subu) is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS )
Subramanian S. Iyer (Subu) is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS ) Prior to Joining UCLA in 2015, he was an IBM Fellow and managed the system integration effort at IBM. His interests lie in developing new integration paradigms that will allow for radically new system architectures.


15th International SoC Conference 2017 - Abstracts & Bios

socconference.com [cached]

Dr. Subramanian S. Iyer, Distinguished Chancellor's Professor
Charles P. Reames Endowed Chair, Electrical Engineering Department, Henry Samueli School of Engineering and Applied Science, UCLA. Bio: Subramanian S. Iyer (Subu) is Distinguished Chancellors Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). He obtained his B.Tech. from IIT-Bombay, and Ph.D. from UCLA and joined the IBM T.J. Watson Research Center at Yorktown heights, NY and later moved to the IBM systems and Technology Group at Hopewell Junction, NY where he was appointed IBM Fellow and was till recently Director of the Systems Scaling Technology Department. His key technical contributions have been the development of the worlds first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBMs development partners to make the first generation smartphone devices. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. His current technical interests and work lie in the area of advanced packaging and three-dimensional integration for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices including hardware security and supply-chain integrity. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow and a Distinguished Lecturer of the IEEE EDS as well as its treasurer. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.


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