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Wrong Subramanian Iyer?

Dr. Subramanian S. Iyer



Direct Phone: (310) ***-****       

Email: s***@***.edu

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405 Hilgard Ave

Los Angeles, California 90095

United States

Company Description

UCLA Anderson Forecast is one of the most widely watched and often-cited economic outlooks for California and the nation and was unique in predicting both the seriousness of the early-1990s downturn in California and the strength of the state's rebound si ... more

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Background Information


IBM Fellow, Director System Scaling Technology
IBM Corporation

Sibond Inc

IBM Fellow
System Technology Group Inc

Fellow Microelectronics Division, IBM Systems& Technology Group Venue
Chief Technologist & IBM


Indian Institutes of Technology

Bachelor of Technology in Electrical Engineering

Indian Institute of Technology , Bombay


Electrical Engineering

University of California at Los Angeles




Electrical Engineering

University of California at Los Angeles

Web References (77 Total References)

Subramanian S. ... [cached]

Subramanian S. Iyer

University of California Los Angeles, USA

14th International System-on-Chip (SoC) Conference - October 19 & 22, 2016 - Keynotes [cached]

Dr. Subramanian S. Iyer, Distinguished Chancellor's Professor Charles P. Reames Endowed Chair, Electrical Engineering Department, Henry Samueli School of Engineering and Applied Science, UCLA.

"A Different Approach to SoCs"
Bio: Subramanian S. Iyer (Subu) is Distinguished Chancellor's Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department at the University of California at Los Angeles and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). He obtained his B.Tech. from IIT-Bombay, and Ph.D. from UCLA and joined the IBM T.J. Watson Research Center at Yorktown heights, NY and later moved to the IBM systems and Technology Group at Hopewell Junction, NY where he was appointed IBM Fellow and was till recently Director of the Systems Scaling Technology Department. His key technical contributions have been the development of the world's first SiGe base HBT, Salicide, electrical Fuses, embedded DRAM and 45nm technology used at IBM and IBM's development partners to make the first generation smartphone devices. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. He has published over 300 papers and holds over 70 patents. His current technical interests and work lie in the area of advanced packaging and three-dimensional integration for system-level scaling and new integration and computing paradigms as well as the long-term semiconductor and packaging roadmap for logic, memory and other devices including hardware security and supply-chain integrity. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow and a Distinguished Lecturer of the IEEE EDS as well as its treasurer. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012. He also studies Sanskrit in his spare time.

14th International SoC Conference 2016 - Agenda [cached]

Professor Subramanian S. Iyer, Center for Heterogeneous Integration and Performance Scaling (CHIPS), Henry Samueli School of Engineering, Electrical Engineering Department, University of California at Los Angeles.

ECTC | IEEE Electronic Components and Technology Conference [cached]

Subramanian Iyer - University of California, Los Angeles

Subramanian Iyer, ... [cached]

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department-and a former fellow and director of the systems scaling technology department at IBM-sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation.

SE: Advanced packaging is being viewed as a way to extend scaling in the future. What's your view?
Iyer: There are a few key things happening.
Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million.
Iyer: That has been the model for shrinking features in a silicon chip.
Iyer: Any time you build a new SoC, you're basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before.
Iyer: We're going to make these pieces hard IP.
Iyer: That's one of the big technology projects. We're looking at it.
Iyer: SerDes speed has been going up exponentially.
Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements.
SE: Then what happens to the package?
Iyer: You have to ask yourself, what is this package really doing?
Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we're going to test these die at full spec.
SE: So what happens without a package?
Iyer: You get rid of a huge amount of space.
Iyer: By replacing the board with a silicon wafer.
Iyer: In one sense, yes, because you can optimize the technology for each die-let.
Iyer: Yes.
Iyer: The supply chain does become more complicated.
Iyer: That's the million-dollar question.
Iyer: An interposer doesn't eliminate the package.

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