Subramanian Iyer, a director of IBM's manufacturing-process development, estimates it takes 1.5 nanoseconds -- or billionths of a second -- to fetch data from its enhanced DRAM technology, compared with 10 to 12 nanoseconds for conventional DRAMs and 0.8 to 1 nanoseconds for SRAMs.Mr. Iyer
said three times more data can be stored in the same amount of space by switching from SRAM to DRAM circuitry; he
expects the technology to be incorporated on microprocessors that will be manufactured next year using a new production process.
..."Processors are definitely cache starved, and as you go more towards multi-core processors, the need for memory integration becomes more acute," said Subramanian Iyer, a distinguished engineer and director of 45nm technology development at IBM.
"There are some server chips that could not be made without this technology," he
In a paper at the International Solid State Circuits Conference here Wednesday (Feb. 14) IBM
will describe a 65nm prototype embedded DRAM with a latency of just 1.5 ns and a cycle time of 2 ns.That's an order of magnitude faster than today's DRAMs and competitive with SRAM that is typically used for microprocessor cache memory.
"To put 24-36 Mbytes of memory on a chip, you would need a 600mm-squared die today.Using this technology you could put that much memory on a 300-350mm-squared die," Iyer
expects to use the technique on its future Power and Cell processors as well as have it available for its ASIC customers."It's being defined in a way that it can be part of our standard 45nm process technology," Iyer
combined two advances to enable the new memory integration.The company found a way to migrate its deep trench technology used for DRAMs from CMOS to its silicon-on-insulator (SOI) logic process.In a paper last December, IBM
described that work that involved suppressing the floating-body effect in SOI.
"Our entire processor road map is based on SOI," said Iyer
New circuit designs use short bit lines to eliminate the need for sense amps that detect voltage differences between the bit lines and a capacitor, a process that makes DRAMs relatively slow.The new design uses a three-transistor micro-sense amp that lets voltage current directly drive transistor gates. IBM
used embedded DRAM in a custom processor designed for its high-end Blue Gene/L supercomputers, but has not been able to use the technology in mass market computer chips to date."This is 100 percent mainstream and we expect to get it in products in 2008," Iyer