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2016-06-03T00:00:00.000Z

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Wrong Subramanian Iyer?

Dr. Subramanian Iyer S.

Distinguished Chancellor's Professor

UCLA

Direct Phone: (310) ***-****       

Email: s***@***.edu

UCLA

325 Westwood Plaza

Los Angeles, California 90095

United States

Company Description

Founded in 1949, UCLA School of Law is the youngest major law school in the nation and has established a tradition of innovation in its approach to teaching, research and scholarship. With approximately 100 faculty and 970 students, the school pioneered c... more

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Background Information

Employment History

IBM Fellow, Director System Scaling Technology

IBM Corporation

Affiliations

IBM Fellow
Systems and Technology Group

Founder
Sibond Inc

Education



Indian Institutes of Technology

Ph.D.

UCLA

Ph.D.
Electrical Engineering
University of California at Los Angeles

Web References (83 Total References)


ECTC | IEEE Electronic Components and Technology Conference

www.ectc.net [cached]

Subramanian Iyer - University of California, Los Angeles


Subramanian Iyer, ...

semiengineering.com [cached]

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department-and a former fellow and director of the systems scaling technology department at IBM-sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation.

SE: Advanced packaging is being viewed as a way to extend scaling in the future. What's your view?
Iyer: There are a few key things happening.
...
Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million.
...
Iyer: That has been the model for shrinking features in a silicon chip.
...
Iyer: Any time you build a new SoC, you're basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before.
...
Iyer: We're going to make these pieces hard IP.
...
Iyer: That's one of the big technology projects. We're looking at it.
...
Iyer: SerDes speed has been going up exponentially.
...
Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements.
SE: Then what happens to the package?
Iyer: You have to ask yourself, what is this package really doing?
...
Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we're going to test these die at full spec.
SE: So what happens without a package?
Iyer: You get rid of a huge amount of space.
...
Iyer: By replacing the board with a silicon wafer.
...
Iyer: In one sense, yes, because you can optimize the technology for each die-let.
...
Iyer: Yes.
...
Iyer: The supply chain does become more complicated.
...
Iyer: That's the million-dollar question.
...
Iyer: An interposer doesn't eliminate the package.


Prof. Subramanian Iyer: ...

www.ieeeottawa.ca [cached]

Prof. Subramanian Iyer: Distinguished Chancellor's Professor, Dept. of EE, UCLA, Los Angeles


Subramanian Iyer - Director ...

www.gsaglobal.org [cached]

Subramanian Iyer - Director & Chief Technologist, Semiconductor Research & Development Center


ECTC | IEEE Electronic Components and Technology Conference

www.ectc.net [cached]

Subramanian Iyer - GLOBALFOUNDRIES

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