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This profile was last updated on 3/5/16  and contains information from public web pages and contributions from the ZoomInfo community.

Dr. Subramanian S. Iyer

Wrong Dr. Subramanian S. Iyer?

Distinguished Chancellor's Profes...

UCLA , Los Angeles
Phone: (310) ***-****  
Email: s***@***.edu
325 Westwood Plaza
Los Angeles , California 90095
United States

Company Description: Founded in 1949, UCLA School of Law is the youngest major law school in the nation and has established a tradition of innovation in its approach to teaching,...   more

Employment History

  • Chancellor's, Professor, Department
  • Adjunct Professor of Electrical Engineering
    Columbia University
  • Fellow and Chief Technologist
    IBM Corporation
  • Manager
    Exploratory Structures and Devices Group

Board Memberships and Affiliations


  • Indian Institutes of Technology
  • Ph.D.
  • Ph.D. , Electrical Engineering
    University of California at Los Angeles
80 Total References
Web References
Subramanian Iyer, ... [cached]
Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department-and a former fellow and director of the systems scaling technology department at IBM-sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation.
SE: Advanced packaging is being viewed as a way to extend scaling in the future. What's your view?
Iyer: There are a few key things happening.
Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million.
Iyer: That has been the model for shrinking features in a silicon chip.
Iyer: Any time you build a new SoC, you're basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before.
Iyer: We're going to make these pieces hard IP.
Iyer: That's one of the big technology projects. We're looking at it.
Iyer: SerDes speed has been going up exponentially.
Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements.
SE: Then what happens to the package?
Iyer: You have to ask yourself, what is this package really doing?
Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we're going to test these die at full spec.
SE: So what happens without a package?
Iyer: You get rid of a huge amount of space.
Iyer: By replacing the board with a silicon wafer.
Iyer: In one sense, yes, because you can optimize the technology for each die-let.
Iyer: Yes.
Iyer: The supply chain does become more complicated.
Iyer: That's the million-dollar question.
Iyer: An interposer doesn't eliminate the package.
Prof. Subramanian Iyer: ... [cached]
Prof. Subramanian Iyer: Distinguished Chancellor's Professor, Dept. of EE, UCLA, Los Angeles
EDS Board of Governors (BoG) | IEEE Electron Devices Society [cached]
• Treasurer: Subramanian S. Iyer
News - 2004 — IITBHF & IITBAA ( [cached]
The details are being worked out, says Subramanian Iyer, IBM's Manager, Embedded Chip Development.
Benefits will accrue to IBM, says Iyer. "The lab will help us network among bright students and attract the best talent. ... Iyer, an IIT alumnus (Electrical Engineering, class of 1977), is currently working on Blue Gene, which, IBM claims, will be the world's most powerful computer when it's completed in 2005.
Wavante [cached]
"Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don't believe that," said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. "I believe at same node you can have two [different variations]," he said in a keynote here.
Iyer of IBM said TSMC's decision to offer one flavor of 20 nm may have been more of an economic than a technical decision.
The historic challenge of offering variations of a process is that each one requires a different set of unique and complex features added to the base process, said Iyer of IBM. "All the little features we have are like drugs, we can't drop them without severe withdrawal symptoms," he said.
"This 3-D technology is really powerful and we will see it in many places," said Iyer of IBM which has already made working prototypes of server processors in TSV stacks with DRAMs.
CPUs have 8-12 cores now "and want to go to 24 cores" with 3-D IC modules that stack DRAMs and heat sinks. IBM is also interested in "systems on an interposer," 2.5-D modules that surround a processor with memory chips on a silicon substrate with de-coupling capacitors to improve power regulation, he said.
"There's a lot of good stuff happening in this area that will make a significant difference, and the same concepts are applicable in the mobile space with similar advantages," he added.
The bad news is "as you go to smaller nodes the benefits of scaling are being eroded significantly," said Iyer of IBM.
The culprit is the lack of any new lithography techniques. Today's 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features.
"This does not come free, the costs are becoming formidable," Iyer said. "Complex patterning solutions are the cause of the angst we are having," he added.
"Until we get to 7 nm or so there are no fundamental issues we see," said Iyer.
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