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This profile was last updated on 8/22/14  and contains information from public web pages and contributions from the ZoomInfo community.

Dr. Subramanian S. Iyer

Wrong Dr. Subramanian S. Iyer?


Phone: (845) ***-****  
Email: s***@***.com
Local Address:  New York , United States
IBM Corporation
1 New Orchard Road
Armonk , New York 10504
United States

Company Description: International Business Machines Corporation (IBM), is an information technology (IT) company. s major operations include Global Technology Services segment (GTS),...   more

Employment History

  • Director of Manufacturing - Process Development
    IBM Corporation
  • Director of 45nm and eTechnologies
    IBM Corporation
  • Director and Chief Technologist
    Semiconductor Research and Development Center
  • Manager
    Exploratory Structures and Devices Group

Board Memberships and Affiliations


  • Ph.D.
  • Ph.D. , Electrical Engineering
    University of California at Los Angeles
65 Total References
Web References
Subramanian Iyer, a director ..., 14 Feb 2007 [cached]
Subramanian Iyer, a director of IBM's manufacturing-process development, estimates it takes 1.5 nanoseconds -- or billionths of a second -- to fetch data from its enhanced DRAM technology, compared with 10 to 12 nanoseconds for conventional DRAMs and 0.8 to 1 nanoseconds for SRAMs.Mr. Iyer said three times more data can be stored in the same amount of space by switching from SRAM to DRAM circuitry; he expects the technology to be incorporated on microprocessors that will be manufactured next year using a new production process.
"Processors are definitely cache starved, and as you go more towards multi-core processors, the need for memory integration becomes more acute," said Subramanian Iyer, a distinguished engineer and director of 45nm technology development at IBM."There are some server chips that could not be made without this technology," he added.
In a paper at the International Solid State Circuits Conference here Wednesday (Feb. 14) IBM will describe a 65nm prototype embedded DRAM with a latency of just 1.5 ns and a cycle time of 2 ns.That's an order of magnitude faster than today's DRAMs and competitive with SRAM that is typically used for microprocessor cache memory.
"To put 24-36 Mbytes of memory on a chip, you would need a 600mm-squared die today.Using this technology you could put that much memory on a 300-350mm-squared die," Iyer said.
IBM expects to use the technique on its future Power and Cell processors as well as have it available for its ASIC customers."It's being defined in a way that it can be part of our standard 45nm process technology," Iyer said.
IBM combined two advances to enable the new memory integration.The company found a way to migrate its deep trench technology used for DRAMs from CMOS to its silicon-on-insulator (SOI) logic process.In a paper last December, IBM described that work that involved suppressing the floating-body effect in SOI.
"Our entire processor road map is based on SOI," said Iyer.
New circuit designs use short bit lines to eliminate the need for sense amps that detect voltage differences between the bit lines and a capacitor, a process that makes DRAMs relatively slow.The new design uses a three-transistor micro-sense amp that lets voltage current directly drive transistor gates.
IBM used embedded DRAM in a custom processor designed for its high-end Blue Gene/L supercomputers, but has not been able to use the technology in mass market computer chips to date."This is 100 percent mainstream and we expect to get it in products in 2008," Iyer said.
IBM, Samsung Move Closer to Next-Gen Mobile Chips - Computer Business Review [cached]
"We can continue to get more cost effective through scaling," said Subramanian Iyer, director of 45nm and eTechnologies at IBM."For low-power technology, we,re able to get roughly 30% more performance at the same power level, and density improvement of 2x ... so roughly, therefore, half the size."
In other words, IBM and its partners can get twice as many chips per silicon wafer using 45-nm technology."So we can get more function per dollar," Iyer added.
Iyer said the group of companies developed several new techniques to overcome such problems.
One such technique was akin to squeezing a water hose to increase the flow of water: The engineers applied tensile stress on the circuitry channel to give the electrons greater mobility.A nitride film was stretched over the channel to apply this stress, Iyer said.
Iyer declined to comment on Intel,s progress.
Part of the reason chipmakers have historically pushed mobile applications, such as cell phones, to market first for their new, smaller chips is because they are high-volume.As process nodes become smaller, the engineering costs to develop new chips grow.That means chipmakers need to sell greater volumes of chips at each new node.
Iyer denied the companies would be required to sell more 45-nm chips to recoup their costs compared to the volume required with 65-nm."As long as you can fill your [chip-making] capacity," he said.
Iyer said the group of chipmakers also was working on two other types of 45-nm processes: an intermediate-performance technology for desktops and notebooks; and a high-performance technology for servers and mainframes.He said he could not comment on launch dates for these, but said they would be later than the low-powered, mobile technology.
The companies have pooled their research and development resources in the past: their current 65-nm node was also jointly developed.More than 200 engineers in total from the four companies have worked intensively on the 45-nm technology announced yesterday, Iyer said.
Subramanian S. Iyer | IEEE Electron Devices Society, 10 May 2012 [cached]
Subramanian S. Iyer
Subramanian S. Iyer
Subramanian S. Iyer is IBM Fellow and Chief Technologist at the Microelectronics Division, IBM Systems & Technology Group, and is responsible for technology strategy and competitiveness, embedded memory and 3 Dimensional Integration.
He obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. He has been with the IBM Microelectronics Division since 1997. Dr. Iyer has received two Corporate awards and four Outstanding Technical Achievement awards at IBM for the development of the Titanium Salicide process, the fabrication of the first SiGe Heterojunction Bipolar Transistor, the development of embedded DRAM technology and the development of eFUSE technology.
His current technical interests and work lie in the area of 3-dimensional integration for memory sub-systems and the semiconductor roadmap. He is a Master Inventor. He received the Distingushed Aluminus award from the Indian Institute of Technology, Bombay in 2004. Dr. Iyer has authored over 175 articles in technical journals and several book chapters and co-edited a book on bonded SOI. He has served as an Adjunct Professor of Electrical Engineering at Columbia University, NY. He is the recepient of the 2012 IEEE Daniel Nobel award for emerging techologies.
In his spare time, he studies Sanskrit and role of Indic languages, traditions and culture in different parts of the world.
Subramanian Iyer - Director ..., 1 June 2014 [cached]
Subramanian Iyer - Director & Chief Technologist, Semiconductor Research & Development Center
News - 2004 — IITBHF & IITBAA ( [cached]
The details are being worked out, says Subramanian Iyer, IBM's Manager, Embedded Chip Development.
Benefits will accrue to IBM, says Iyer. "The lab will help us network among bright students and attract the best talent. ... Iyer, an IIT alumnus (Electrical Engineering, class of 1977), is currently working on Blue Gene, which, IBM claims, will be the world's most powerful computer when it's completed in 2005.
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