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Wrong Subramanian Iyer?

Dr. Subramanian S. Iyer

Distinguished Chancellor's Professor


Direct Phone: (310) ***-****       

Email: s***@***.edu

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405 Hilgard Ave

Los Angeles, California 90095

United States

Company Description

UCLA Anderson Forecast is one of the most widely watched and often-cited economic outlooks for California and the nation and was unique in predicting both the seriousness of the early-1990s downturn in California and the strength of the state's rebound si ... more

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Background Information

Employment History

IBM Fellow, Director System Scaling Technology

IBM Corporation


IBM Fellow
System Technology Group Inc

Fellow Microelectronics Division, IBM Systems& Technology Group Venue
Chief Technologist & IBM

Sibond Inc


Indian Institutes of Technology

Bachelor of Technology in Electrical Engineering

Indian Institute of Technology , Bombay


Electrical Engineering

University of California at Los Angeles




Electrical Engineering

University of California at Los Angeles

Web References (87 Total References)

ECTC | IEEE Electronic Components and Technology Conference [cached]

Subramanian Iyer - University of California, Los Angeles

Subramanian Iyer, ... [cached]

Subramanian Iyer, distinguished chancellor's professor in UCLA's Electrical Engineering Department-and a former fellow and director of the systems scaling technology department at IBM-sat down with Semiconductor Engineering to talk about the future of chip scaling. What follows are excerpts of that conversation.

SE: Advanced packaging is being viewed as a way to extend scaling in the future. What's your view?
Iyer: There are a few key things happening.
Iyer: The non-recurring engineering charge for a new fairly basic SoC is, at a minimum, $30 million to $50 million.
Iyer: That has been the model for shrinking features in a silicon chip.
Iyer: Any time you build a new SoC, you're basically taking everything that has previously been done, and doing it again on a piece of silicon and interconnecting it all. About 90% of an SoC has existed in some form before.
Iyer: We're going to make these pieces hard IP.
Iyer: That's one of the big technology projects. We're looking at it.
Iyer: SerDes speed has been going up exponentially.
Iyer: We can make them highly parallelized without necessarily going to higher-speed interconnects. That lowers the power and the area requirements.
SE: Then what happens to the package?
Iyer: You have to ask yourself, what is this package really doing?
Iyer: It allows us to test the chip. That function it does quite well. Anything that gets rid of the package needs to comprehend how we're going to test these die at full spec.
SE: So what happens without a package?
Iyer: You get rid of a huge amount of space.
Iyer: By replacing the board with a silicon wafer.
Iyer: In one sense, yes, because you can optimize the technology for each die-let.
Iyer: Yes.
Iyer: The supply chain does become more complicated.
Iyer: That's the million-dollar question.
Iyer: An interposer doesn't eliminate the package.

Prof. Subramanian Iyer: ... [cached]

Prof. Subramanian Iyer: Distinguished Chancellor's Professor, Dept. of EE, UCLA, Los Angeles

13th International System-on-Chip (SoC) Conference - October 21 & 22, 2015 - Keynotes [cached]

Dr. Subramanian S. Iyer, Distinguished Chancellor's Professor Charles P. Reames Endowed Chair, Electrical Engineering Department, Henry Samueli School of Engineering and Applied Science, UCLA.

Bio: Subramanian S. Iyer's pioneering development of embedded dynamic random access memory (eDRAM) has boosted the power of computer processors for applications ranging from high-end servers to gaming consoles and personal electronics. Dr. Iyer recognized the need for large amounts of high-density, high-performance, and high-bandwidth memory placed close to the integrated circuit to fully exploit the power of computer processors. His eDRAM technology allows for integration of very large amounts of dense on-chip memory with significantly lower power and higher reliability compared to conventional methods. The on-chip memory solution has enabled more memory to be placed on smaller chips, resulting in systems with higher performance. Dr. Iyer has been the driving force in IBM's commercialization of eDRAM, guiding it through all stages of development, and it has also become a standard feature of IBM's application-specific integrated circuits.
An IEEE Fellow and IBM Fellow, Dr. Iyer is chief technologist with the Microelectronics Division of IBM's Systems & Technology Group in Hopewell Junction, New York, where he is responsible for technical strategy, embedded memory, and three-dimensional integration.

Subramanian Iyer - Director ... [cached]

Subramanian Iyer - Director & Chief Technologist, Semiconductor Research & Development Center

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